Global Standards for the Microelectronics Industry
Memory Configurations: JESD21-C
JESD21-C, JEDEC Configurations for Solid State Memories, is a compilation of some 3000 pages of all memory device standards for solid state memory including DIMM, DRAM, SDRAM, MCP, PROM, and others from September 1989 to present. The document is divided into sections for ease of use. Each section can be searched by following one of the links listed on the menu "JESD21-C Standards" on the right of this page.
The JEDEC JC-42 Committee on RAM Memory and its Subcommittees, JC-45 Committee on Memory Modules and its Subcommittees and the JC-63 Committee on Multi Chip Packages develop the standards in JESD21-C and are responsible for updating the publication.
An annual updating service for JESD21 is available by subscription. Subscribers receive periodic electronic updates for replacement or insertion into the hard copy JESD21-C.
A complete hard copy of JESD21-C is available for purchase. The hard copy comes in two 3” wide 3-ring binders so that future updates can be added with ease.
- JESD21-C: Table of Contents
- Section 1: Scope
- Section 2: Terms and Definitions
- Section 3: General
- Section 6: Applicable Other Documents
- Annexes: Differences between revisions
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Related Committees and Subcommittees
| JC-42 | Solid State Memories |
| JC-42.2 | SRAM Memories |
| JC-42.3 | DRAM Memories |
| JC-42.3B | Functions, Features and Pinouts |
| JC-42.3C | DRAM Parametrics |
| JC-42.3D | DRAM Pinouts |
| JC-42.4 | Non-Volatile Memory Devices |
| JC-42.6 | Low Power Memories |
| JC-45 | DRAM Modules |
| JC-45.1 | Registered DRAM Modules |
| JC-45.2 | Unbuffered DRAM Modules |
| JC-45.3 | Unbuffered DRAM Modules |
| JC-45.4 | Fully Buffered DRAM Modules |
| JC-45.5 | Module Interconnect |
| JC-63 | Multiple Chip Packages |