Server Forum Agenda

Onsite Check-in Desk Open - Preregistrants Only

Charles Furnweger, JEDEC

Welcome Remarks
Mian Quddus, Chairman, JEDEC Board of Directors

Morning Keynotes

Server Memory Architecture: Emerging Trends and Challenges
Presenter: John Halbert, Intel

10:00-10:30AM
 

Next Gen Memory Driving Server Performance & Growth
Next Generation Memory will be critical to meeting future Server performance requirements. We continue to experience high levels of demand growth and increased diversification within the Server market, driving the need for more advanced technologies. With this diversification, comes a need for standardization and timely migration to Next Gen Memory. DDR5 & NVDIMM-P will facilitate these growth trends and performance requirements.
Presenter: Jim Elliott, Samsung

Overcoming System Memory Challenges with Persistent Memory and NVDIMM-P
The IT industry is now encountering significant technology disruptions that may even change the basic computing architecture used now for several decades.  This session will give an overview of the significant challenges for memory in the datacenter systems, introduce the upcoming NVDIMM-P memory module type, and highlight some of the ways persistent memory can be used to solve these imminent problems.
Presenter: Bill Gervasi, Discobolus Designs

Morning Session

NVDIMM-P Architecture and Protocol

This session will cover architecture and protocol direction for NVDIMM-P modules.  These modules share the same channel with DDR4 or DDR5 and provides system access to non-volatile, or persistent memory.  In order to access media which may have non-deterministic latencies a transactional protocol with handshaking has been defined.  Other aspects of the protocol will cover out of order transactions, persistent writes, flush commands, link protection, cache management on memory modules etc.
Presenter: Kuljit Bains, Qualcomm

Enabling NVDIMM-P and Storage Class Memory Ecosystem

With the ever-increasing need for more efficient memory solutions, NVDIMM-P is being defined as the new standard protocol for storage class memory. Having the right standard is important, but additional actions need to be taken, such as media (device) selection, caching/tiering application identification, and SW/HW ecosystem development.  This presentation will cover Samsung's view on these topics as well as a call to action for the industry partners.
Presenter: Indong Kim, Samsung

Afternoon Keynotes

Server Memory Requirements in the Cognitive Era
While server memory must continue its historical trajectory of capacity and bandwidth growth, more types of devices now need to be attached to a processor to meet the diversity of server applications deployed across today's on-premise and cloud environments. Diversification of memory technology is also imminent. These factors drive the need for a common standard interface which is agnostic to device type, device technology and processor architecture, and the DDR5 Differential solution will fulfill such a need.

Presenter: KH Kim, IBM

Server Memory in the Age of the Cloud
The challenges and solutions for memory modules as the world migrates to the cloud.  Maximizing performance, density, channel resources, and expanding memory types all while balancing low power and low cost demands from the solution providers.

Presenter: Desi Rhoden, Montage

Afternoon Session

How JEDEC Builds the Memory of Tomorrow, Today!
Join Cox as he walks you through how JEDEC never stands still and is constantly working with the entire memory ecosystem to define next generation memory technologies.  Cox will focus on how the multinational, multi-organizational group is working on our next server memory, DDR5, and explore some of the new functions of DDR5 as wells as why they are important for the current and emerging server segments.
Presenter: Chris Cox, Intel

DDR5 Commands (Command Truth Table)

With the continuing trend of increasing processor core counts along with more diverse server workloads comes rising demand for memory capacity and memory bandwidth. These demands are in the context of ongoing
challenges in DRAM process scaling and interface signaling. The DDR5 specification is being developed to accomplish the goals of supporting increased memory performance and flexibility for systems of the future. One
key enabling feature of DDR5 is its command interface, which differs in many
ways from previous DDR devices. This presentation will give an overview of
DDR5’s command interface showing some of the new functionality and how
it solves many of the challenges being faced.

Presenter: Matt Prather, Micron

DDR5 PMIC on DIMM – New Industry Direction and Update
Memory sub-system power delivery in Server system has become increasingly more complex with each generation of DDR memory technology. Server system continues to increase the memory capacity and bandwidth while keeping the constant DIMM power envelope and reducing the cost of memory sub-system. While DRAM continues to scale the process technology to address the memory capacity and performance requirement, there is significant burden on DRAM with legacy power delivery scheme and significant challenges to reduce the memory sub-system cost. A new change in memory sub-system power delivery is needed to address DDR5 server system requirements. This presentation discusses the new approach in DDR5 technology for power delivery. It highlights the challenges associated with existing power delivery scheme and the advantages of new power delivery scheme.
Presenter: Sam Patel, IDT

How Measurement Science Informs the DDR5 Standard
Over time, as DDR speeds have increased, the fundamental approach used to move data has had to change.   Traditional High Speed Digital timing and noise with min/typ/max specifications gave way in DDR4 to High Speed Serial approaches based on eye masks with random and deterministic noise and jitter specifications.   DDR5 must go a step further to deal with closed eyes using tunable equalization with the standard describing limits on the impulse response of the Tx/bus/Rx channel.    At each point the need to characterize and measure what’s defined in the standard has made Measurement Science and DFT increasingly important in defining the DDR standard.  This session will focus on the Measurement Science behind the DDR5 standard.

Presenter: Perry Keller, Keysight