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Displaying 1 - 10 of 10 documents. Show 5 results per page.

Title	Document #	Date
TWO-RESISTOR COMPACT THERMAL MODEL GUIDELINE	JESD15-3	Jul 2008
This document specifies the definition and construction of a two-resistor compact thermal model (CTM) from the JEDEC junction-to-case and junction-to-board thermal metrics. The guidance provided in this document only applies to thermal metrics defined in JEDEC standards JESD51-8 and JESD51-12. The scope of this document is limited to single-die packages that can be effectively represented by a single junction temperature. Committee(s): JC-15 Free download. Registration or login required.
THERMAL MODELING OVERVIEW	JESD15	Oct 2008
This document and the associated series of documents are intended to promote the continued development of modeling methods, while providing a coherent framework for their use by defining a common vocabulary to discuss modeling, creating requirements for what information should be included in a thermal modeling report, and specifying modeling procedures, where appropriate, and validation methods. This document provides an overview of the methodology necessary for performing meaningful thermal simulations for packages containing semiconductor devices. The actual methodology components are contained in separate detailed documents. Committee(s): JC-15, JC-15.1 Free download. Registration or login required.
Standard Practices and Procedures - Reflow Flatness Requirements for Ball Grid Array Packages. Item 11.2-783	SPP-024A	Mar 2009
This document states the procedures for using component land side flatness during simulated reflow as an alternative to coplanarity in certain limited cases for BGA components. Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
COMPACT THERMAL MODEL OVERVIEW	JESD15-1	Oct 2008
This document should be used in conjunction with the master document, JESD15, and JESD15-2, and subsidiary documents as they become available. This document is intended to function as an overview to support the effective use of Compact Thermal Model (CTM) methodologies as specified in the companion methods documents. At present, there are two such documents; JESD15-3, and JESD15-4. Committee(s): JC-15, JC-15.1 Free download. Registration or login required.
DELPHI COMPACT THERMAL MODEL GUIDELINE	JESD15-4	Oct 2008
This guideline specifies the definition and lists acceptable approaches for constructing a compact thermal model (CTM) based on the DELPHI methodology. The purpose of this document is twofold. First, it aims to provide clear guidance to those seeking to create DELPHI compact models of packages. Second, it aims to provide users with an understanding of the methodology by which they are created and validated, and the issues associated with their use. Committee(s): JC-15 Free download. Registration or login required.
PACKAGE WARPAGE MEASUREMENT OF SURFACE-MOUNT INTEGRATED CIRCUITS AT ELEVATED TEMPERATURE	JESD22-B112A	Oct 2009
The purpose of this test method is to measure the deviation from uniform flatness of an integrated circuit package body for the range of environmental conditions experienced during the surface-mount soldering operation. Committee(s): JC-14.1, JC-14 Free download. Registration or login required.
THERMAL TEST ENVIRONMENT MODIFICATIONS FOR MULTICHIP PACKAGES	JESD51-31	Jul 2008
This document specifies the appropriate modifications needed for Multi-Chip Packages to the thermal test environmental conditions specified in the JESD51 series of specifications. The data obtained from methods of this document are the raw data used to document the thermal performance of the package. The use of this data will be documented in JESD51-XX, Guideline to Support Effective Use of MCP Thermal Measurements which is being prepared. Committee(s): JC-15 Free download. Registration or login required.
Registration - Upper PoP Package, Square, Fine Pitch, Ball Grid Array (BGA), 0.65 and 0.50 mm and 0.40 mm Pitch. POP-XFBGA.	MO-273C	Mar 2011
Item 11.11-841 Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Plastic Small Outline Package with Exposed Heat Sink.	MO-230-A	Mar 2001
Item 11.11-574 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 204 Pin DDR3 SODIMM w/ 0.60 mm Pitch. DIM	MO-268E	Mar 2014
Item 11.14-151 Patents(): Hatachi: 5,227,664 Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.

Standards & Documents Search

TWO-RESISTOR COMPACT THERMAL MODEL GUIDELINE

THERMAL MODELING OVERVIEW

Standard Practices and Procedures - Reflow Flatness Requirements for Ball Grid Array Packages. Item 11.2-783

COMPACT THERMAL MODEL OVERVIEW

DELPHI COMPACT THERMAL MODEL GUIDELINE

PACKAGE WARPAGE MEASUREMENT OF SURFACE-MOUNT INTEGRATED CIRCUITS AT ELEVATED TEMPERATURE

THERMAL TEST ENVIRONMENT MODIFICATIONS FOR MULTICHIP PACKAGES

Registration - Upper PoP Package, Square, Fine Pitch, Ball Grid Array (BGA), 0.65 and 0.50 mm and 0.40 mm Pitch. POP-XFBGA.

Registration - Plastic Small Outline Package with Exposed Heat Sink.

Registration - 204 Pin DDR3 SODIMM w/ 0.60 mm Pitch. DIM

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