Global Standards for the Microelectronics Industry
Dictionary D
D(n)(x)
See "data input".
References:D; d
See "drain terminal".
References:DAC
See "digital-to-analog [D/A] converter".
References:dark condition
The condition attained when the electrical parameter under consideration approaches a value that cannot be altered by further irradiation shielding.
References:JESD77-B, 2/00
dark current spike
A variation of the dark current that exceeds some specified level above the average value.
References:JESD99B, 5/07
Darlington transistor
A compound semiconductor device consisting of two transistors in which the collectors are connected together and the emitter of the first transistor is connected to the base of the second transistor.
NOTE 1 The two transistors connected in this manner may be regarded as a compound transistor with three terminals.
NOTE 2 The circuit may include a biasing network.
NOTE 3 The presence of a terminal to provide direct access to the base of the second transistor is optional.
Graphic symbols (ref. IEEE Std 315):
NOTE In the graphic symbols, the envelope is optional if no element is shown connected to the envelope.
References:JESD77-B, 2/00
data bar polling
A method, used to determine whether the write operation in a memory is complete, wherein the memory is put into the read mode after initiating the write mode; if writing is complete, the outputs take on the addressed stored data, or if writing is not complete, the specified output(s) take on the complement of the last bit(s) written.
NOTE If writing is not complete: (a) in older devices, normally all outputs take on the complement of the last bits written; (b) in more modern byte-wide memories, only the most significant output takes on the complement of the last bit written; (c) in word-wide memories, the most significant output of the least significant byte, the most significant output of the entire word, or both of these outputs take on the complement of the last bit written.
References:JESD100-B, 12/99
data bus
A bus used to communicate data internally and externally to and from processing units, storage devices, or peripheral devices. (Adapted from ANSI X3.172.)
References:JESD100-B, 12/99
data change
An event in which at least one bit of data is caused to change.
NOTE This event may be used as a unit of endurance for erasable programmable read-only memories.
References:JESD100-B, 12/99
data cycle
A cycle in which each bit changes to its opposite state and back to its original state.
NOTE 1 These changes may occur for all bits in parallel or in series, e.g., by page, block, word, byte, or bit.
NOTE 2 This cycle may be used as a unit of endurance for erasable programmable read-only memories.
References:JESD100-B, 12/99
data input [D(n)(x)]
Those inputs whose states represent the data that is to be written into the selected address on a write cycle of an alterable memory device. When the numbering of the data inputs is significant for device operation, the data inputs are numbered beginning with 0. In devices where data bit groupings have independent control, an additional suffix "x" is applied. "x" takes the values of a, b, c, etc.
References:JESD21-C, 1/97
data input/output [DQ(n)(x)]
The pins that serve as data output(s) when in the read mode and as data input(s) when in the write mode. When the device is not selected or enabled, the output(s) are in a floating state. On devices having both serial and parallel access ports, these pins provide access to the parallel RAM port data channels. The suffix (n) is a numeric value indicating the number assignment of a particular pin with numbering starting at 0. In some situations the letter "U" or "L" is used to indicate that the pins are assigned to the upper or lower byte of a two-byte data interface. In devices where the standard supports an optional 9th bit that may be used as a parity bit, the suffix P may be used in lieu of a numeric value. In devices where data bit groupings have independent control, an additional suffix "x" is applied. "x" takes the values of a, b, c, etc.
References:JESD21-C, 1/97
data output [Q(n)(x)]
The outputs whose states represent the data read from the selected cells. When the device is not selected or enabled, the outputs are usually in a floating (Z, high-impedance) state. When the numbering of the data outputs is significant for device operation, the data outputs are numbered beginning with 0. In devices where data bit groupings have independent control, an additional suffix "x" is applied. "x" takes the values of a, b, c, etc.
References:JESD21-C, 1/97
data pattern
The mix of 1s and 0s in the memory and their physical or logical positions.
References:JESD22-A117A, 3/06
data rewrite
An operation including one data cycle or at least one data change, in which data is written into an array.
References:JESD100B.01, 12/02
data-retention mode
A standby or battery mode of operation in which the integrity of stored data is maintained although the supply voltage is below that specified for reading or writing.
References:JESD100-B, 12/99
data-retention supply current (of an SRAM offering a data-retention mode) (ICC(DR), IDD(DR), etc.)
The supply current in the data-retention mode.
References:JESD99B, 5/07